module PulseGenerator(in,clk,rst,out);
	input		in;
	input		clk;
	input		rst;
	output		out;
	reg			d_out1;
	reg			d_out2;
	
	assign out = d_out1 & (!d_out2);
	
	always @(posedge clk or negedge rst) begin
		if(!rst) begin
			d_out1 <= 0;
			d_out2 <= 0;
		end
		else begin
			d_out1 <= in;
			d_out2 <= d_out1;
		end
	end

endmodule